This Section will cover the internals of Interrupt Handling in Linux Kernel (all explaination is related to i386 platform). This section is under development and might be incomplete right now.

I will cover the following topics in this section, explaining thehardware as well as software part of it, from how the interrupts aregenerated, routed and then handled by the low level code of Linux Kernel.

- Introduction - CPU Support for Handling Interrupts

- Details of Programmable Interrupt Controller - Hardware checks performed by CPU

- Details of Interrupt Descriptor Table

- Task Gates - Trap Gates - Interrupt Gates

- Kernel Support for Handling Interrupts

- Low Level Interrupt Stubs - Details of do_IRQ() function, core of Inteuupt Handling

__'''Introduction'''__ 

This section will discuss, the hardware prospective of interrupt handling fromCPU, Linux Kernel's Interrupt Routing subsystem, Device Drivers's rolein Interrupt handling.

Term __Interrupt__ is self defined,Interrupts are signals sent to CPU on an INTR bus (connected to CPU) whenever any device want to get attention of CPU. As soon as theinterrupt signal occurs, CPU defer the current activity and service the interrupt by executing the interrupt handler corresponding to that interrupt number (also know as IRQ number).

One of the clasifications of Interrupts can be done as follows: - Synchronous Interrupts (also know on as software interrupts) - Asynchronous Interrupts (also know as hardware interrupts)

Basic difference between these is that, synchronous interrupts are generated by CPU's control unit on facing some abnormal condition; these are also know as exception in Intel's termenology. These are interrupts whihc are generated by CPU itself either when CPU detects an abnormal condition or CPU executes some of the special instructions like 'int'or 'int3' etc. on other hand, asynchronous interupts are those, which actually are generated by outside world (devices connected to CPU). As these interrupts can occur at any point of time, these are known asynchronous interrupts.

Its important to note that both synchornous and asynchronous interrupts are handled by CPU on the completion of insturction during which the interrupt occur. Execution of a machine instruction is not done in one single CPU cycle, it take somecycles to complete. Any interrupt occurs in between the execution of instruction, will not be handled imediately, rather CPU will check o finterrupts on the completion of instruction.

'''__CPU's support for handling interrupts__'''

For handling interrupts there are few of the things which we expect theCPU to do on occurence of every interrupt. Whenever an interrupt occurs,CPU performs some of the hardware checks, which are very much needed tomake the system secure. Before explaining the hardware checks, we willunderstand how the interrupts are routed to the CPU from hardwaredevices.

 '''''Details of Programmable Interrupt Controller'''''
On Intel architecture, system devices (device controllers) areconnected to a special device known as PIC (Programmable Interrupt Controller). CPU have two lines for receiving interrupt signals (NMIand INTR). NMI line is to recieve non-maskable interrupts; the interrupts which can not be masked, means which can not be blocked atany cost. These interrupts are of hightest priority and are rarelyused. INTR line is the line on which all the interrupts from system devices are received. These interrupts can be masked or blocked. As allthe interrupt signals need to be multiplxed on single CPU line, we needsome mechanisum through which interrupts from different device controllers can be routed to single line of CPU. This routing or multiplexing is done PIC (Programmable Interrupt Controller). PIC sits between system devices and CPU and have multiple input lines; each line connected to different divice contollers in system. On other hand IPC have only one output line which is connected to the CPU's INTR line on which it sends signal to CPU.

 There are two PIC controllers joined together and the output of second PIC controller is connected tothe second input of first PCI. This setup allows maximum of 15 input lines on which different system device controllers can be connected. PIC have some programmable registers, through which CPU communicates with it (give command, mask/unmask interrup lines, read status). Both PICs have their own following registers:

 - Mask Register
- Status Register

 Mask register is used to mask/unmask a specific interrupt line. CPU can ask the PIC to mask (block) the specific interrupt by setting the corresponding bit in mask register. Unmasking can be done by clearing that bit. When a particular interrupt is being masked, PIC do receive the interrupts on its corresponding input line, but do not send the interrupt singnal to CPU in which case CPU keeps on doing what it was doing. When an interrupts are being masked, they are not lost, rather PIC remembers those and do send the interrupt to CPU when CPU unmasks that interrupt line. Masking is different from blocking all the interrupts toCPU. CPU can ignore all the interrupts coming on INTR line by clearing the IF (Interrupt Falg) flag in EFLAGS register of CPU. When this bit is cleared, interrupts coming on INTR line are simply ignored by CPU, we can consider it to be blocking of interrupts. So now we understand that masking is done at PIC level and individual interrupt lines can be masked or unmasked,where as blocking is done at CPU level and is done for all the interrupts coming to taht CPU except NMI (Non-Maskable Interrupt), which is received on NMI line of CPU and can not be blocked or ignored.

 Now days,interrupt architecture is not as simple as shown above. Now days machines uses the APIC (Advanced Programmable Interrupt Controller), which can support upto 256 interrupt lines. Along with APIC, every CPU also have inbuilt IO-APIC. I won't go into details of these right now.

 '''''Hardware checks performed by CPU'''''
Once the interrupt signal is received by CPU, CPU performs some hardware checks for which no software machine instructions are executed. Before looking into what these checks are, we need to understand some architecture spcific data structures maintained by kernel.

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